The present invention relates, in general, to the field of broadband radio frequency (RF) modems and methods for intertransmission of data on a local network thereof. More particularly, the present invention relates to a frequency agile, phase continuous, frequency shift keyed (FSK) modulator and method for non-return to zero (NRZ) and other data utilizing dual modulus phase locked loop (PLL) frequency synthesis. A common use for such a modulator is in broadband RF modems as well as other communications equipment.
In the past, PLL's have been utilized as a frequency synthesizer for the transmit and receive functions of RF modems and other transceivers. PLL synthesizers are utilized to contol an oscillator, usually a VCO, by means of a digitally coded input to the PLL synthesizer for generation of an error signal to the oscillator. Generally, FSK modulation is used as opposed to amplitude (AM) or phase (PM) modulation techniques.
Certain prior art circuits generate FSK data by employing two oscillators, each generating an output at a different frequency, and providing means for switching back and forth between the oscillators in response to whether the digital serial data input signal is low or high. Such prior art circuits suffer from several limitations including the fact that in order to change the output frequencies, i.e., to switch between different subchannels, multiple pairs of oscillators must be used. Additionally, these prior art circuits generate undesirable AM sidebands as the oscillators are switched on and off.
An alternative concept is disclosed in U.S. Pat. No. 3,902,013 issuing to Charbonnier on Aug. 26, 1975 for a "Frequency Synthesis Control for a Frequency-Modulated Telegraphic Transmitter". This patent presents an extremely complex system and fails to show any direct modulation of a VCO with the NRZ data stream, instead requiring a coding matrix responsive to the data input. Additionally, this patent fails to show any mechanism for switching between channels in a broadband RF system and contemplates use of a programmable counter/divider.
An additional concept is described in U.S. Pat. No. 3,993,868 issuing to Balcewicz on Nov. 23, 1976 for a "Minimum Shift Keying Communications System". This patent describes a communications system utilizing a pair of PLL's, each generating a different frequency. The device switches between these PLL's to transmit a "minimum shift keying" FSK encoded signal. As above described with respect to the U.S. Pat. No. 3,902,013, there is neither a disclosure of any direct modulation of the VCO by a serial data input stream nor is any mechanism disclosed for switching between channels.
Other patents illustrative of prior art techniques include U.S. Pat. No. 3,787,775 issuing to Lanning on Jan. 22, 1974 for a "Phase Correction Circuit" and describing a demodulator for phase shift keying; U.S. Pat. No. 3,860,874 issuing to Malone et al. on Jan. 14, 1975 for a "Receiver for DFSK Signals" showing a demodulator for double FSK data; and U.S. Pat. No. 4,335,446 issuing to Gandini et al. on June 15, 1982 for "Terminal Equipment for Data-Transmission Network Including Digitally Operating Modem" illustrative of the technique of differential phase shift keying.